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rev 1.1 1/10 copyright ? 2010 by silicon laborato ries si4030/31/32 si4030/31/32-b1 si4030/31/32 ism t ransmitter features applications description silicon laboratories? si403 0/31/32 devices are highly integrated, single-chip wireless ism transmitters. the high-performance ezradiopro ? family includes a complete line of transmitte rs, receivers, and transceivers allowing the rf system designer to choose the optimal wire less part for their application. the si4030/31/32 offers advanced radio features including continuous frequency coverage from 240?960 mhz with adjustable power output levels of ?8 to +13 dbm on the si4030/31 and +1 to +20 dbm on the si4032. power adjustments are made in 3 db steps. the si4030/31 /32?s high level of integration offers reduced bom cost while si mplifying the overall syst em design. the si4032?s industry leading +20 dbm output power ensures extended range and improved link performance. additional system features such as an automatic wake-up timer, low battery detector, 64 byte tx fifo, and automatic packet handling reduce overall current consumption and al low the use of lower-cost system mcus. an integrated temperature sensor, general purpose adc, power-on-reset (por), and gpios further reduce overall system cost and size. the direct digital transmit modulation and automatic pa power ramping ensure precise transmit modulation and reduc ed spectral spreading ensuring compliance with global regulations including fcc, etsi, and arib regulations. an easy-to-use calculator is provided to quickly configure the radio settings, simplifying customer's system design and reducing time to market. ? frequency range ?? 240?930 mhz (si4031/32) ?? 900?960 mhz (si4030) ? output power range ?? +1 to +20 dbm (si4032) ?? ?8 to +13 dbm (si4030/31) ? low power consumption ?? si4032 85 ma @ +20 dbm ?? si4030/31 30 ma @ +13 dbm ? data rate = 0.123 to 256 kbps ? fsk, gfsk, and ook modulation ? power supply = 1.8 to 3.6 v ? ultra low power shutdown mode ? wake-up timer ? integrated 32 khz rc or 32 khz xtal ? integrated voltage regulators ? configurable packet handler ? tx 64 byte fifo ? low battery detector ? temperature sensor and 8-bit adc ? ?40 to +85 c temperature range ? integrated voltage regulators ? frequency hopping capability ? on-chip crystal tuning ? 20-pin qfn package ? low bom ? power-on-reset (por) ? remote control ? home security & alarm ? te l e m e t r y ? personal data logging ? toy control ? wireless pc peripherals ? remote meter reading ? remote keyless entry ? home automation ? industrial control ? sensor networks ? health monitors patents pending ordering information: see page 53. pin assignments gnd pad 1 2 3 17 18 19 20 11 12 13 14 6 7 8 9 4 5 16 10 15 xout vr_dig sclk sdi sdo vdd_dig nc vdd_rf nc gpio_2 gpio_1 nc tx nc nirq sdn xin nsel gpio_0 nc si4030/31/32
si4030/31/32-b1 2 rev 1.1 functional block diagram
si4030/31/32-b1 rev 1.1 3 t able of c ontents section page 1. electrical specificat ions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 1.1. definition of test conditi ons . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2. functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 2.1. operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3. controller interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3.1. serial peripheral interfac e (spi) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3.2. operating mode control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3.3. interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 3.4. system timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3.5. frequency control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 4. modulation options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 4.1. modulation type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 4.2. modulation data source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 5. internal functional blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 1 5.1. synthesizer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 5.2. power amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 1 5.3. crystal oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 5.4. regulators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33 6. data handling and packet handl er . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 6.1. tx fifo . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 6.2. packet configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35 6.3. packet handler tx mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35 6.4. data whitening, manchester en coding, and crc . . . . . . . . . . . . . . . . . . . . . . . . . . 37 6.5. synchronization word conf iguration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 6.6. tx retransmission and auto tx . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 7. auxiliary functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 7.1. smart reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 7.2. microcontroller clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40 7.3. general purpose adc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 7.4. temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42 7.5. low battery detector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44 7.6. wake-up timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 7.7. gpio configurat ion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 8. reference design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48 9. application notes and reference desi gns . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 10. customer support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49 11. register table and descripti ons . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 12. pin descriptions : si4030/31/32 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 13. ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52
si4030/31/32-b1 4 rev 1.1 14. package markings (top marks) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 14.1. si4030/31/32 top mark . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 14.2. top mark explanation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 15. package outline: si4030/ 31/32 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 16. pcb land pattern: si4030/31/32 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 document change list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 contact information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58
si4030/31/32-b1 rev 1.1 5 l ist of f igures figure 1. spi timing...... ................ ................ .............. .............. ............... .............. ............. ...... 15 figure 2. spi timing?read m ode .............. ................. ................ ................. ................ ..........16 figure 3. spi timing?burst write mode ............. ................. .............. .............. .............. .......... 16 figure 4. spi timing?burst read mode .. .............. .............. .............. .............. .............. .......... 16 figure 5. state machine diagram......... ................ ................. .............. .............. .............. .......... 17 figure 6. tx timing........... ................. ................ ................ ................. ................ ................ ...... 21 figure 7. frequency de viation ............... .............. .............. .............. ............... .............. ............ 2 5 figure 8. fsk vs. gfsk spectr ums................. ................ ................ ................. .............. ..........27 figure 9. microcontroller connections.... ................. .............. .............. .............. .............. .......... 30 figure 10. pll synthesizer block diagram ................. ................. ................ ................. ............ 31 figure 11. fifo threshold .............. ................. ................ .............. .............. .............. .............. .34 figure 12. packet structure............. ................. ................ .............. .............. .............. ............. .. 35 figure 13. multiple packets in tx pa cket handler ................ .............. .............. .............. .......... 36 figure 14. operation of da ta whitening, manchester encoding , and crc ............. ................. 37 figure 15. manchester coding example ... .............. .............. .............. .............. .............. ..........37 figure 16. por glitch parameters....... ................ ................. .............. .............. .............. .......... 39 figure 17. general purpose ad c architecture .. ................ ................. .............. .............. .......... 41 figure 18. temperature ranges using adc8 ........... .............. .............. .............. .............. ........ 43 figure 19. wut interrupt and wut operat ion................. ................ ................. .............. .......... 46 figure 20. si4031 reference design schematic ............. ................ ................. .............. .......... 48 figure 21. 20-pin quad flat no-lead (qfn) ... ................ ................ ................. .............. ..........54 figure 22. pcb land pattern ...... ................ ................ ................. ................ ................. ............ 5 5
si4030/31/32-b1 rev 1.1 6 l ist of t ables table 1. dc characteristics 1 ................. ................. .............. .............. .............. .............. ............7 table 2. synthesizer ac el ectrical characteristics 1 ................. ............... .............. ........... ..........8 table 3. transmitter ac el ectrical characteristics 1 ................. ............... .............. ........... ..........9 table 4. auxiliary block specifications 1 ................. .............. .............. .............. .............. ..........10 table 5. digital io specifications (sdo, sdi, sclk, nsel, and nirq) .. .............. ........... ........ 11 table 6. gpio specifications (gpio_0, gpio _1, and gpio_2) ................. ................. ............ 11 table 7. absolute maximum ra tings ................. ................ ................. .............. .............. .......... 12 table 8. operating modes ..... ................ ................. ................ ................. ................ ............... ..14 table 9. serial interface ti ming parameters .............. ................. ................ ................. ............15 table 10. operating modes response ti me ................. ................ ................. ................ ..........17 table 11. frequency band selection ....... .............. .............. .............. .............. .............. .......... 23 table 12. packet handler registers ......... .............. .............. .............. .............. .............. .......... 36 table 13. por parameters ............... ................ ................ .............. ............... .............. ............ 39 table 14. temperature sensor range ................... .............. .............. .............. .............. .......... 42 table 15. register descriptions ................. ................ ................. ................ ................. ............ 50 table 16. package dimensions ........... ................ ................. .............. .............. .............. .......... 54 table 17. pcb land pattern di mensions ............ ................. .............. .............. .............. .......... 56
si4030/31/32-b1 rev 1.1 7 1. electrical specifications table 1. dc characteristics 1 parameter symbol conditions min typ max units supply voltage range v dd 1.8 3.0 3.6 v power saving modes i shutdown rc oscillator, main digital regulator, and low power digital regulator off 2 ?15 50 na i standby low power digital regulator on (register values retained) and main digital regulator, and rc oscillator off ? 450 800 na i sleep rc oscillator and low power digital regulator on (register values retained) and main digital regulator off ?1 ?a i sensor-lbd main digital regulator and low battery detector on, crystal oscillator and all other blocks off 2 ?1 ?a i sensor-ts main digital regulator and temperature sensor on, crystal oscillator and all other blocks off 2 ?1 ?a i ready crystal oscillator and main digital regulator on, all other blocks off. crystal oscillator buffer disabled ?800 ? a tune mode current i tune synthesizer and regulators enabled ? 8.5 ? ma tx mode current ?si4032 i tx_+20 txpow[2:0] = 111 (+20 dbm) using silicon labs? reference design. tx current consumption is dependent on match and board layout. ?85 ? ma tx mode current ?si4030/31 i tx_+13 txpow[2:0] = 111 (+13 dbm) using silicon labs? reference design. tx current consumption is dependent on match and board layout. ?30 ? ma i tx_+1 txpow[2:0] = 011 (+1 dbm) using silicon labs? reference design. tx current consumption is dependent on match and board layout. ?18 ? ma notes: 1. all specification guaranteed by production test unless otherwise noted. prod uction test conditions and max limits are listed in the "production test conditions" section on page 13. 2. guaranteed by qualification. q ualification test conditions are listed in the "production test conditions" section on page 13.
si4030/31/32-b1 8 rev 1.1 table 2. synthesizer ac electrical characteristics 1 parameter symbol conditions min typ max units synthesizer frequency range?si4031/32 f syn 240 ? 930 mhz synthesizer frequency range?si4030 f syn 900 ? 960 mhz synthesizer frequency resolution 2 f res-lb low band, 240?480 mhz ? 156.25 ? hz f res-hb high band, 480?960 mhz ? 312.5 ? hz reference frequency input level 2 f ref_lv when using external reference signal driving xout pin, instead of using crystal. measured peak-to-peak (v pp ) 0.7 ? 1.6 v synthesizer settling time 2 t lock measured from exiting ready mode with xosc running to any frequency. including vco calibration. ?200? s residual fm 2 ? f rms integrated over ? 250 khz bandwidth (500 hz lower bound of integration) ?2 4khz rms phase noise 2 l ? (f m ) ? f = 10 khz ? ?80 ? dbc/hz ? f = 100 khz ? ?90 ? dbc/hz ? f = 1 mhz ? ?115 ? dbc/hz ? f = 10 mhz ? ?130 ? dbc/hz notes: 1. all specification guaranteed by production test unless otherwise noted. production test conditions and max limits are listed in the "production test conditions" section on page 13. 2. guaranteed by qualification. qualificati on test conditions are listed in the "p roduction test conditions" section on page 13.
si4030/31/32-b1 rev 1.1 9 table 3. transmitter ac electrical characteristics 1 parameter symbol conditions min typ max units tx frequency range?si4031/32 f tx 240 ? 930 mhz tx frequency range?si4030 f tx 900 ? 960 mhz fsk data rate 2 dr fsk 0.123 ? 256 kbps ook data rate 2 dr ook 0.123 ? 40 kbps modulation deviation f1 860?960 mhz 0.625 320 khz f2 240?860 mhz 0.625 160 khz modulation deviation resolution 2 f res ?0.625? khz output power range ?si4032 3 p tx +1 ? +20 dbm output power range?si4030/31 3 p tx ?8 ? +13 dbm tx rf output steps 2 ? p rf_out controlled by txpow[2:0] ? 3 ? db tx rf output level 2 variation vs. temperature ? p rf_temp ?40 to +85 ? c?2?db tx rf output level variation vs. frequency 2 ? p rf_freq measured across any one frequency band ?1?db transmit modulation filtering 2 b*t gaussian filtering bandwith time product ?0.5? spurious emissions 2 p ob-tx1 p out =13dbm, frequencies <1 ghz ???54dbm p ob-tx2 1?12.75 ghz, excluding harmonics ? ? ?54 dbm harmonics 2 p 2harm using reference design tx matching network and filter with max output power. harmonics reduce linearly with output power. ???42dbm p 3harm ???42dbm notes: 1. all specification guaranteed by producti on test unless otherwise noted. producti on test conditions and max limits are listed in the "production test conditions" section on page 13. 2. guaranteed by qualification. qualification test conditions are listed in the "production test conditions" section on page 13. 3. output power is dependent on matching components and board layout.
si4030/31/32-b1 10 rev 1.1 table 4. auxiliary block specifications 1 parameter symbol conditions min typ max units temperature sensor accuracy 2 ts a after calibrated via sensor offset register tvoffs[7:0] ?0.5?c temperature sensor sensitivity 2 ts s ?5?mv/c low battery detector resolution 2 lbd res ?50?mv low battery detector conversion time 2 lbd ct ?250?s microcontroller clock output frequency f mc configurable to 30 mhz, 15 mhz, 10 mhz, 4 mhz, 3mhz, 2mhz, 1mhz, or 32.768 khz 32.768k ? 30m hz general purpose adc resolution 2 adc enb ?8?bit general purpose adc bit resolution 2 adc res ?4?mv/bit temp sensor & general purpose adc conversion time 2 adc ct ?305?s 30 mhz xtal start-up time t 30m using xtal and board layout in reference design. start-up time will vary with xtal type and board layout. ?600?s 30 mhz xtal cap resolution 2 30m res ?97?ff 32 khz xtal start-up time 2 t 32k ?6?sec 32 khz xtal accuracy using 32 khz xtal 2 32k res using 20 ppm 32 khz crystal ? 100 ? ppm 32 khz accuracy using internal rc oscillator 2 32krc res ?2500?ppm por reset time t por ?16?ms software reset time 2 t soft ?100?s notes: 1. all specification guaranteed by product ion test unless otherwise noted. product ion test conditions and max limits are listed in the "production test conditions" section on page 13. 2. guaranteed by qualification. qualification test conditions are listed in the "production test conditions" section on page 13.
si4030/31/32-b1 rev 1.1 11 table 5. digital io specifications (sdo, sdi, sclk, nsel, and nirq) parameter symbol conditions min typ max units rise time t rise 0.1 x v dd to 0.9 x v dd , c l = 5 pf ? ? 8 ns fall time t fall 0.9 x v dd to 0.1 x v dd, c l = 5 pf ? ? 8 ns input capacitance c in ??1pf logic high level input voltage v ih v dd ?0.6 ? ? v logic low level input voltage v il ?0.6 v input current i in 0=hh ??8ns fall time t fall 0.9 x v dd to 0.1 x v dd, c l = 10 pf, drv<1:0>=hh ??8ns input capacitance c in ??1pf logic high level input voltage v ih v dd ?0.6 ? v logic low level input voltage v il ??0.6v input current i in 0=ll 0.1 0.5 0.8 ma i omaxlh drv<1:0>=lh 0.9 2.3 3.5 ma i omaxhl drv<1:0>=hl 1.5 3.1 4.8 ma i omaxhh drv<1:0>=hh 1.8 3.6 5.4 ma logic high level output voltage v oh i oh < i omax source, v dd =1.8 v v dd ?0.6 ? ? v logic low level output voltage v ol i ol < i omax sink, v dd =1.8 v ??0.6v note: all specifications guaranteed by qualification. qualification test conditions ar e listed in the "production test conditions" section on page 13.
si4030/31/32-b1 12 rev 1.1 table 7. absolute maximum ratings parameter value unit v dd to gnd ?0.3, +3.6 v instantaneous v rf-peak to gnd on tx output pin ?0.3, +8.0 v sustained v rf-peak to gnd on tx outp ut pin ?0.3, +6.5 v voltage on digital control inputs ?0.3, v dd + 0.3 v voltage on analog inputs ?0.3, v dd + 0.3 v operating ambient temperature range t a ?40 to +85 ? c thermal impedance ? ja 30 ? c / w junction temperature t j +125 ? c storage temperature range t stg ?55 to +125 ? c note: stresses beyond those listed under ?absolute maximum ra tings? may cause permanent damage to the device. these are stress ratings only and functional operation of the devic e at or beyond these ratings in the operational sections of the specifications is not implied. exposure to absolute ma ximum rating conditions for extended periods may affect device reliability. power amplifier may be damaged if swit ched on without proper load or termination connected. tx matching network design will influence tx v rf-peak on tx output pin. caut ion: esd sensitive device.
si4030/31/32-b1 rev 1.1 13 1.1. definition of test conditions production test conditions: ? t a =+25c ? v dd =+3.3vdc ? tx output power measured at 915 mhz ? external reference signal (xout) = 1.0 v pp at 30 mhz, centered around 0.8 vdc ? production test schematic (unless noted otherwise) ? all rf output levels referr ed to the pins of the si4030/31/32 (not the rf module) qualification test conditions: ? t a = ?40 to +85 c ? v dd = +1.8 to +3.6 vdc ? using 4032, 4031, or 4030 reference de sign or production test schematic ? all rf output levels referr ed to the pins of the si4030/31/32 (not the rf module)
si4030/31/32-b1 14 rev 1.1 2. functional description the si4030/31/32 are ism wireless transmitters with contin uous frequency tuning over their specified bands which encompasses 240?960 mhz. the wide operating voltage range of 1.8?3.6 v and low current consumption makes the si4030/31/32 an ideal solution for battery powered applications. the rf carrier is generated by an integrated vco and ?? fractional-n pll synthesizer. the synthesizer is designed to support configurable data rates, output freq uency, frequency deviation, and gaussian filtering at any frequency between 240?960 mhz. the transmit fsk data is modulated directly into the ?? data stream and can be shaped by a gaussian low-pass filter to reduce unwanted spectral content. the si4032?s pa output power can be configured between +1 and +20 dbm in 3 db steps, while the si4030/31's pa output power can be configured between ?8 and +13 dbm in 3 db steps. the pa is single-ended to allow for easy antenna matching and low bom cost. the pa incorporates automatic ramp-up and ramp-down control to reduce unwanted spectral spreading. the +20 dbm power am plifier of the si4032 can also be used to compensate for the reduced performance of a lower cost, lower perfor mance antenna or antenna with size constraints due to a small form-factor. compet ing solutions require large and expensiv e external pas to achieve comparable performance. the si4030/31/32 is designed to work with a microcontroller, crystal, and a few external components to create a very low cost system. voltage regulators are integrated on -chip which allows for a wide operating supply voltage range from +1.8 to +3.6 v. a standard 4-pin spi bus is used to communicate with an external microcontroller. three configurable general purpose i/os are available. a co mplete list of the available gpio functions is available in ?an466: si4030/31/32 register descriptions.? 2.1. operating modes the si4030/31/32 provides several operating modes whic h can be used to optimize the power consumption for a given application. table 8 summarizes the operating modes of the si4030 /31/32. in general, any given operating mode may be classified as an active mode or a power saving mode. the table indicates which block(s) are enabled (active) in each corresponding mode. with the exception of the shutdown mode, all can be dynamically selected by sending the appropriate commands over the spi. an ?x? in any cell means that, in the given mode of operation, that block can be independently programmed to be eith er on or off, without noticeably impacting the current consumption. the spi circuit block includes the spi inte rface hardware and the device register space. the 32 khz osc block includes the 32.768 khz rc oscillator or 32.768 khz crystal oscillator and wake-up timer. aux (auxiliary blocks) includes the te mperature sensor, general purpose adc, and low-battery detector. table 8. operating modes mode name circuit blocks digital ldo spi 32 khz osc aux 30 mhz xtal pll pa i vdd shutdown off (register contents lost) off off off off off off 15 na standby on (register contents retained) on off off off off off 450 na sleep on on x off off off 1 a sensor on x on off off off 1 a ready on x x on off off 800 a tuning on x x on on off 8.5 ma transmit on x x on on on 30 ma* *note: using si4030/31 at +13 dbm usin g recommended reference design.
si4030/31/32-b1 rev 1.1 15 3. controller interface 3.1. serial periph eral interface (spi) the si4030/31/32 communicates with the host mcu over a standard 3-wire spi interface: sclk, sdi, and nsel. the host mcu can read data from the device on the sdo ou tput pin. a spi transaction is a 16-bit sequence which consists of a read-write (r /w) select bit, followed by a 7-bit addre ss field (addr), and an 8-bit data field (data) as demonstrated in figure 1. the 7-bit address field is used to select one of the 128, 8-bit control registers. the r /w select bit determines whether the spi transa ction is a read or write transaction. if r /w = 1 it signifies a write transaction, while r /w = 0 signifies a read transaction. the contents (addr or data) are latched into the si4030/31/32 every eight clock cycles. the timing para meters for the spi interface are shown in table 9. the sclk rate is flexible with a maximum rate of 10 mhz. figure 1. spi timing to read back data from the si4030/31/ 32, the r/w bit must be set to 0 follow ed by the 7-bit address of the register from which to read. the 8 bit data field following the 7-bi t addr field is ignored n the sdi pin when r/w = 0. the next eight negative e dge transitions of the sclk signal will clock ou t the contents of the se lected register. the data read from the selected regi ster will be available on the sdo output pin. the read function is shown in figure 2. after the read function is completed the sdo pin will rema in at either a logic 1 or logic 0 state depending on the last data bit clocked out (d0). when nsel goes high the sdo output pin will be pulled high by internal pullup. table 9. serial interface timing parameters symbol parameter min (nsec) diagram t ch clock high time 40 t cl clock low time 40 t ds data setup time 20 t dh data hold time 20 t dd output data delay time 20 t en output enable time 20 t de output disable time 50 t ss select setup time 20 t sh select hold time 50 t sw select high period 80 nsel sclk sdi msb lsb a2 a1 a0 d7 d6 d5 d4 d3 d2 d1 d0 a4 xx xx a3 rw a7 a6 a5 rw data address sdi sclk sdo nsel t cl t ch t ds t dh t dd t ss t e n t sh t de t sw
si4030/31/32-b1 16 rev 1.1 figure 2. spi timing?read mode the spi interface contains a burst read /write mode which allows for reading/ writing sequential registers without having to re-send the spi address. when the nsel bit is held low while continuing to send sclk pulses, the spi interface will automatically increment th e addr and read from/write to the next address. an example burst write transaction is illustrate d in figure 3 and a burst read in figure 4. as long as nsel is held low, input data will be latched into the si4030/31/32 every eight sclk cycles. figure 3. spi timing?burst write mode figure 4. spi timing?burst read mode nsel sclk sdi first bit last bit a0 d7 =x sdo d7 a1 a2 first bit last bit a3 d6 =x d5 =x d4 =x d3 =x d2 =x d1 =x d0 =x d6 d5 d4 d3 d2 d1 d0 a4 a5 a6 rw =0 nsel sclk sdi first bit a0 d7 =x a1 a2 a3 d6 =x d5 =x d4 =x d3 =x d2 =x d1 =x d0 =x a4 a5 a6 rw =1 last bit d7 =x d6 =x d5 =x d4 =x d3 =x d2 =x d1 =x d0 =x nsel sclk sdi first bit last bit a0 d7 =x sdo d7 a1 a2 first bit a3 d6 =x d 5 =x d 4 =x d3 =x d2 =x d1 =x d0 =x d6 d5 d4 d3 d2 d1 d0 a4 a5 a6 rw =0 d7 d6 d5 d4 d3 d2 d1 d0
si4030/31/32-b1 rev 1.1 17 3.2. operating mode control there are three primary states in the si4030/31/32 radio state machine: shutdown, idle, and tx (see figure 5). the shutdown state complete ly shuts down the radio to minimize current consumption. there are five different configurations/options for the idle state which can be selected to optimize the chip to the applications needs. "register 07h. operating mode and function cont rol 1" controls which operat ing mode/state is selected with the exception of shutdown which is controlled by sdn pin 20. the tx state may be reached automatically from any of the idle states by setting the txon bit in "register 07h. operating mode and function control 1." table 10 shows each of the operating modes with the time required to reach tx mode as well as the current consumption of each mode. the si4030/31/32 includes a low-power digital regulated su pply (lpldo) which is inter nally connected in parallel to the output of the main digital regulator (and is ava ilable externally at the vr_dig pin). this common digital supply voltage is connected to all digital circuit blo cks including the spi and regi ster space. the lpldo has extremely low quiescent current consumpt ion but limited current supply capab ility; it is used only in the idle- standby and idle-sleep modes. the main digital regu lator is automatically en abled in all other modes. figure 5. state machine diagram table 10. operating modes response time state/mode response time to tx current in state/mode [a] shut down state 16.8 ms 15 na idle states: standby mode sleep mode sensor mode ready mode tune mode 800 s 800 s 800 s 200 s 200 s 450 na 1a 1a 800 a 8.5 ma tx state na si4032: 85 ma @ +20 dbm, si4030/31: 30 ma @ +13 dbm shut dwn idle* t x * five different options for idle shutdown
si4030/31/32-b1 18 rev 1.1 3.2.1. shutdown state the shutdown state is the lowest current consumption state of the device with nominally less than 15 na of current consumption. the shutdown state may be entere d by driving the sdn pin (pin 20) high. the sdn pin should be held low in all states e xcept the shutdown state. in the shutdown state, the contents of the registers are lost and there is no spi access. when the chip is connected to the power supply, a por will be initiated after the falling edge of sdn. 3.2.2. idle state there are five different modes in the idle state which may be selected by "register 07h. operating mode and function control 1". all modes have a tradeoff between cu rrent consumption and response time to tx mode. this tradeoff is shown in table 10. after the por event, swreset, or exit ing from the shutdown state the chip will default to the idle-ready mode. after a por event the inte rrupt registers must be read to properly enter the sleep, sensor, or standby mode and to control the 32 khz clock correctly. 3.2.2.1. standby mode standby mode has the lowest current consumption of th e five idle states with only the lpldo enabled to maintain the register values. in this mode the regist ers can be accessed in both read and write mode. the standby mode can be entered by writ ing 0h to "register 07h. operatin g mode and function control 1". if an interrupt has occurred (i.e., the nirq pin = 0) the interr upt registers must be read to achieve the minimum current consumption. additionally, the adc should not be selected as an input to th e gpio in this mode as it will cause excess current consumption. 3.2.2.2. sleep mode in sleep mode the lpldo is enabled along with the wake -up-timer, which can be used to accurately wake-up the radio at specified intervals. see "7.6. wake-up timer" on page 45 for more information on the wake-up-timer. sleep mode is entered by se tting enwt = 1 (40h) in "regis ter 07h. operating mode and function control 1". if an interrupt has occurred (i.e., the nirq pin = 0) the interrupt registers must be read to achieve the minimum current consumption. also, the adc sh ould not be selected as an input to the gpio in this mode as it will cause excess current consumption. 3.2.2.3. sensor mode in sensor mode either the low battery detector, temperature sensor, or both may be enabled in addition to the lpldo and wake-up-timer. the low battery detector can be enabled by setting enlbd = 1 in "register 07h. operating mode and function control 1". see "7.4. temperature sensor" on page 42 and "7.5. low battery detector" on page 44 for more information on these features. if an interrupt has occurred (i.e., the nirq pin = 0) the interrupt registers must be read to ac hieve the minimum current consumption. 3.2.2.4. ready mode ready mode is designed to give a fast transition time to tx mode with reasonable current consumption. in this mode the crystal oscillator remains enab led reducing the time required to swit ch to tx mode by eliminating the crystal start-up time. ready mode is entered by setting xton = 1 in "register 07h. operating mode and function control 1". to achieve the lowest curr ent consumption state the crystal osc illator buffer should be disabled in ?register 62h. crystal osc illator control and test.? 3.2.2.5. tune mode in tune mode the pll remains enabled in addition to th e other blocks enabl ed in the idle modes. this will give the fastest response to tx mode as the pll will re main locked but it results in the highest current consumption. this mode of operation is designed for frequency hopp ing spread spectrum syste ms (fhss). tune mode is entered by setting pllon = 1 in "register 07h. operating mode and function control 1". it is not necessary to set xton to 1 for this mode, the internal state mach ine automatically enables the crystal oscillator.
si4030/31/32-b1 rev 1.1 19 3.2.3. tx state the tx state may be entered from any of the idle modes wh en the txon bit is set to 1 in "register 07h. operating mode and function control 1". a built-in sequencer takes care of all the actions re quired to transition between states from enabling the crystal o scillator to ramping up the pa. the following sequence of events will occur automatically when going from standby mode to tx mode by setting the txon bit. 1. enable the main digital ldo and the analog ldos. 2. start up crystal oscillator and wait unt il ready (controlled by an internal timer). 3. enable pll. 4. calibrate vco (this action is skipped when the vcocal bit is ?0?, default value is ?1?). 5. wait until pll settles to required transmit frequency (controlled by timer). 6. activate power amplifier and wait until power rampin g is completed (controlled by an internal timer). 7. transmit packet. steps in this sequence may be eliminated depending on whic h idle mode the chip is configured to prior to setting the txon bit. by default, the vco and pll are calibrated every time the pll is enabled. 3.2.4. device status the operational status of the chip can be read from "register 02h. device status". add r/w function/description d7 d6 d5 d4 d3 d2 d1 d0 por def. 02 r device status ffovfl ffunfl reser ved reserved freqerr cps[1] cps[0] ?
si4030/31/32-b1 20 rev 1.1 3.3. interrupts the si4030/31/32 is capable of generating an interrupt sign al when certain events occur. the chip notifies the microcontroller that an interrupt event has occurred by setting the nirq output pin low = 0. this interrupt signal will be generated when any one (or more) of the interrupt events (corres ponding to the interrupt status bits) shown below occur. the nirq pin will remain low until the microcont roller reads the inte rrupt status regi ster(s) (registers 03h?04h) containing the active interrupt status bit. the nirq output si gnal will then be reset until the next change in status is detected. the interrupts must be enabled by the corresponding enable bit in the interrupt enable registers (registers 05h?06h). all enabled interrupt bits will be cleare d when the microcontroller reads the interrupt status regi ster. if the interrupt is not enab led when the event occurs it will not trigger the nirq pin, but the status may still be read at anytime in the interrupt status registers. see ?an466: si4030/31/32 register descript ions? for a complete list of interrupts. add r/w function/descript ion d7 d6 d5 d4 d3 d2 d1 d0 por def. 03 r interrupt status 1 ifferr itxffafull itx ffaem reserved iext ipksent reserved reserved ? 04 r interrupt status 2 reserved reserved reserved reserved iwut ilbd ichiprdy ipor ? 05 r/w interrupt enable 1 enfferr entxffafull entxf faem reserved enext enpksent reserved reserved 00h 06 r/w interrupt enable 2 reserved reserved r eserved reserved enwut enlbd enchiprdy enpor 01h
si4030/31/32-b1 rev 1.1 21 3.4. system timing the system timing for tx mode is shown in figure 6. the figures demonstrate transitioning from standby mode to tx mode through the built-in sequencer of required st eps. the user only needs to program the desired mode, and the internal sequ encer will properly transition t he part from its current mode. the vco will automatically calibrate at every frequency change or power up. the pll t0 time is to allow for bias settling of the vco. the pll ts time is for the settling ti me of the pll, which has a default setting of 100 s. the total time for pll t0, pll cal, and pll ts under all co nditions is 200 s. under certain applications, the pll t0 time and the pll cal may be skipped for faster turn-arou nd time. contact applications support if faster turnaround time is desired. figure 6. tx timing tx packet xtal settling time pll t0 pll cal pllts 600us configurable 0-70us, default = 50us 50us, may be skipped pre pa ramp pa ramp up pa ramp down configurable 0-310us, recommend 100us 6us, fixed configurable 5-20us, recommend 5us 1.5bits @dr configurable 5-20us, recommend 5us
si4030/31/32-b1 22 rev 1.1 3.5. frequency control for calculating the necessar y frequency register settings it is re commended that custom ers use silicon labs? wireless design suite (wds) or the ezradiopro register calculator worksheet (in microsoft excel) available on the product website. these methods offe r a simple method to quickly determi ne the correct settings based on the application requirements. the following information can be used to calculated these values manually. 3.5.1. frequency programming in order to transmit an rf signal, the desired channel frequency, f carrier , must be programmed into the si4030/31/32. note that this frequency is the center frequency of the desired channel. the carrier frequency is generated by a fractional-n synthesi zer, using 10 mhz both as the reference frequency and the clock of the (3 rd order) ? modulator. this modulator uses modulo 64000 accumulators. this design was made to obtain the desired frequency resolution of the synthesizer. the overall division ratio of the feedback loop consist of an integer part (n) and a fractional part (f).in a generic sense, the output frequency of the synthesizer is as follows: the fractional part (f) is determined by three differ ent values, carrier frequency (fc[15:0]), frequency offset (fo[8:0]), and frequency deviation (fd[7:0]). due to the fi ne resolution and high loop bandwidth of the synthesizer, fsk modulation is applied inside the loop and is done by varying f according to the incoming data; this is discussed further in "3.5.4. frequency deviation" on page 24. also, a fixed offset can be added to fine-tune the carrier frequency and counteract crystal tolerance errors. for simplicity a ssume that only the fc[15:0] register will determine the fractional component. the equation for selection of the carrier frequency is shown below: the integer part (n) is determined by fb[4:0]. additio nally, the output frequency can be halved by connecting a 2 divider to the output. this divider is not inside the loop and is controlled by the hbsel bit in "register 75h. frequency band select". this effect ively partitions the entire 240?960 mhz frequency range into two separate bands: high band (hb) for hbsel = 1, and low band (lb) for hbsel = 0. the valid range of fb[4:0] is from 0 to 23. if a higher value is written into the regist er, it will default to a value of 23. th e integer part has a fixed offset of 24 added to it as shown in the formula above. table 11 demonstrates the selection of fb[4:0] for the corresponding frequency band. after selection of the fb (n) the fractional component may be solved with the following equation: fb and fc are the actual numbers stor ed in the corresponding registers. add r/w function/description d7 d6 d5 d4 d3 d2 d1 d0 por def. 73 r/w frequency offset 1 fo[7] fo[6] fo[5] fo[4] fo[3] fo[2] fo[1] fo[0] 00h 74 r/w frequency offset 2 fo[9] fo[8] 00h 75 r/w frequency band select sbsel hbsel fb[4] fb[3] fb[2] fb[1] fb[0] 35h 76 r/w nominal carrier frequency 1 fc[15] fc[14] fc[13] fc[12] fc[11] fc[10] fc[9] fc[8] bbh 77 r/w nominal carrier frequency 0 fc[7] fc[6] fc[5] fc[4] fc[3] fc[2] fc[1] fc[0] 80h ) ( 10 f n mhz f out ? ? ? ) ( ) 1 ( 10 f n hbsel mhz f carrier ? ? ? ? ? ) 64000 ] 0 : 15 [ 24 ] 0 : 4 [ ( * ) 1 ( * 10 fc fb hbsel mhz f tx ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? fb hbsel mhz f fc tx
si4030/31/32-b1 rev 1.1 23 table 11. frequency band selection fb[4:0] value n frequency band hbsel=0 hbsel=1 0 24 240?249.9 mhz 480?499.9 mhz 1 25 250?259.9 mhz 500?519.9 mhz 2 26 260?269.9 mhz 520?539.9 mhz 3 27 270?279.9 mhz 540?559.9 mhz 4 28 280?289.9 mhz 560?579.9 mhz 5 29 290?299.9 mhz 580?599.9 mhz 6 30 300?309.9 mhz 600?619.9 mhz 7 31 310?319.9 mhz 620?639.9 mhz 8 32 320?329.9 mhz 640?659.9 mhz 9 33 330?339.9 mhz 660?679.9 mhz 10 34 340?349.9 mhz 680?699.9 mhz 11 35 350?359.9 mhz 700?719.9 mhz 12 36 360?369.9 mhz 720?739.9 mhz 13 37 370?379.9 mhz 740?759.9 mhz 14 38 380?389.9 mhz 760?779.9 mhz 15 39 390?399.9 mhz 780?799.9 mhz 16 40 400?409.9 mhz 800?819.9 mhz 17 41 410?419.9 mhz 820?839.9 mhz 18 42 420?429.9 mhz 840?859.9 mhz 19 43 430?439.9 mhz 860?879.9 mhz 20 44 440?449.9 mhz 880?899.9 mhz 21 45 450?459.9 mhz 900?919.9 mhz 22 46 460?469.9 mhz 920?939.9 mhz 23 47 470?479.9 mhz 940?960 mhz
si4030/31/32-b1 24 rev 1.1 3.5.2. easy frequency programming for fhss while registers 73h?77h may be used to program the carrie r frequency of the si4030/31/3 2, it is often easier to think in terms of ?channels? or ?channel numbers? rath er than an absolute frequency value in hz. also, there may be some timing-critical applications (such as for frequen cy hopping systems) in whic h it is desirable to change frequency by programming a single register. once the chan nel step size is set, the frequency may be changed by a single register corresponding to the channel number. a nominal frequency is first set using registers 73h?77h, as described above. registers 79h and 7ah are then used to set a channel step size and channel number, relative to the nominal setting. the frequency hopping step size (f hs[7:0]) is set in increments of 10 khz with a maximum channel step size of 2.56 mhz. the frequency hopping channel select register then selects channels based on multiples of the step size. for example, if the nominal frequency is set to 900 mhz using registers 73h?77h, the channel step size is set to 1 mhz using "register 7ah. frequency hopping step si ze," and "register 79h. frequency hopping channel select" is set to 5d, the resulting carrier frequency would be 905 mhz. once the nominal frequency and channel step size are programmed in the registers, it is only necessary to program the fhch[7:0] register in order to change the frequency. 3.5.3. automatic state transition for frequency change if registers 79h or 7ah are changed in tx mode, the state ma chine will automatically tr ansition the chip back to tune and change the frequency. this fe ature is useful to reduce the number of spi commands required in a frequency hopping system. this in tu rn reduces microcontroller activity, reducing current consumption. the exception to this is during tx fifo mode. if a frequency change is initiated during a tx packet, then the part will complete the curr ent tx packet and will only change th e frequency for s ubsequent packets. 3.5.4. frequency deviation the peak frequency deviation is configurable from 0.625 to 320 khz. the frequency deviation ( f) is controlled by the frequency deviation register (fd), address 71 and 72h, and is independent of the carrier frequency setting. when enabled, regardless of the setting of the hbsel bit (high band or low band), the resolution of the frequency deviation will remain in increm ents of 625 hz. when using frequency modu lation the carrier fr equency will deviate from the nominal center channel carrier frequency by f: add r/w function/description d7 d6 d5 d4 d3 d2 d1 d0 por def. 79 r/w frequency hopping channel select fhch[7] fhch[6] fhch[5 ] fhch[4] fhch[3] fhch[2] fhch[1] fhch[0] 00h 7a r/w frequency hopping step size fhs[7] fhs[6] fhs[5] fhs[4] fh s[3] fhs[2] fhs[1] fhs[0] 00h ) 10 ] 0 : 7 [ ( ] 0 : 7 [ khz fhch fhs fnom f carrier ? ? ? ? hz f fd 625 ] 0 : 8 [ ? ? ? f peak deviation = hz fd f 625 ] 0 : 8 [ ? ? ?
si4030/31/32-b1 rev 1.1 25 figure 7. frequency deviation the previous equation should be used to calculate t he desired frequency deviation. if desired, frequency modulation may also be disabled in order to obtain an un modulated carrier signal at the channel center frequency; see "4.1. modulation type" on page 27 for further details. add r/w function/description d7 d6 d5 d4 d3 d2 d1 d0 por def. 71 r/w modulation mode control 2 trclk[1] trclk[0 ] dtmod[1] dtmod[0] eninv fd[8] modtyp[1] modtyp[0] 00h 72 r/w frequency deviation fd[7] fd[6] f d[5] fd[4] fd[3] fd[2] fd[1] fd[0] 20h frequency f carrier time f
si4030/31/32-b1 26 rev 1.1 3.5.5. frequency offset adjustment a frequency offset can be adjusted manually by fo[9:0] in registers 73h and 74h. the frequency offset adjustment is implemented by shifting the synthesizer lo cal oscillator frequency. this register is a signed regist er so in order to get a negative offset it is necessary to take the twos co mplement of the positive offs et number. the offset can be calculated by the following: the adjustment range in high band is 160 khz and in lo w band it is 80 khz. for example to compute an offset of +50 khz in high band mode fo[9:0] should be set to 0a0h. for an offset of ?50 khz in high band mode the fo[9:0] register should be set to 360h. 3.5.6. tx data rate generator the data rate is configurable between 0.123?256 kbps. for data rates below 30 kbps the ?txdtrtscale? bit in register 70h should be set to 1. when higher data rates are used this bit should be set to 0 . the tx date rate is de termined by the follo wing formula in kbps: add r/w function/descript ion d7 d6 d5 d4 d3 d2 d1 d0 por def. 73 r/w frequency offset fo[7] fo[6] fo[5] fo[4] fo[3] fo[2] fo[1] fo[0] 00h 74 r/w frequency offset fo[9] fo[8] 00h add r/w function/description d7 d6 d5 d4 d3 d2 d1 d0 por def. 6e r/w tx data rate 1 txdr[15] txdr[14] txdr[13] txdr[12] txdr[11] txdr[10] txdr[9] txdr[8] 0ah 6f r/w tx data rate 0 txdr[7] txdr[6] txdr[ 5] txdr[4] txdr[3] txdr[2] txdr[1] txdr[0] aah ] 0 : 9 [ ) 1 ( 25 . 156 fo hbsel hz set desiredoff ? ? ? ? ) 1 ( 25 . 156 ] 0 : 9 [ ? ? ? hbsel hz set desiredoff fo dr_tx (kbps) txdr 15:0 ?? 1 mhz ? 2 16 5 txdtrtscale ? + --------------------------------------------------- = txdr[15:0] dr_tx(kbps) 2 16 5 txdtrtscale ? + ? 1 mhz ---------------------------------------------------------------------------------------- =
si4030/31/32-b1 rev 1.1 27 4. modulation options 4.1. modulation type the si4030/31/32 supports three different modulation options: gaussian frequency shift keying (gfsk), frequency shift keying (fsk), and on-off keying (o ok). gfsk is the recommended modulation type as it provides the best performance and cleanest modulati on spectrum. figure 8 demonstr ates the difference between fsk and gfsk for a data rate of 64 kbps. the time domain plots demonstrate the effects of the gaussian filtering. the frequency domain plots demonstrate the spectral benefit of gfsk over fsk. the type of modulation is selected with the modtyp[1:0] bits in "register 71h. modulation mode cont rol 2." note that it is also possible to obtain an unmodulated carrier signal by setting modtyp[1:0] = 00. figure 8. fsk vs. gfsk spectrums modtyp[1:0] modulation source 00 unmodulated carrier 01 ook 10 fsk 11 gfsk (enable tx data clk when direct mode is used) tx modulation time domain waveforms -- fsk vs. gfsk -1.0 -0.5 0.0 0.5 1.0 -1.5 1.5 sigdata_fsk[0,::] 50 100 150 200 250 300 350 400 450 050 0 -0.5 0.0 0.5 -1.0 1.0 time, usec sigdata_gfsk[0,::] tx modulation spectrum -- fsk vs gfsk (continuous prbs) -80 -60 -40 -100 -20 modspectrum_fsk -200 -150 -100 -50 0 50 100 150 200 -250 250 -80 -60 -40 -100 -20 freq, khz modspectrum_gfsk datarate 64000.0 txdev 32000.0 bt_filter 0.5 modindex 1.0
si4030/31/32-b1 28 rev 1.1 4.2. modulati on data source the si4030/31/32 may be configured to obtain its modulation data from one of three different sources: fifo mode, direct mode, and from a pn9 mode. in direct mode, the tx modulation data may be obtained from several different input pins. these options are set through the dtm od[1:0] field in "register 7 1h. modulation mode control 2." 4.2.1. fifo mode in fifo mode, the transmit data is stored in integrat ed fifo register memory. the fifos are accessed via "register 7fh. fifo access," and are most efficiently ac cessed with burst read/write operation as discussed in "3.1. serial peripheral interface (spi)" on page 15. in tx mode, the data bytes stored in fifo memory ar e "packaged" together with other fields and bytes of information to construct the final transm it packet structure. these other potent ial fields include the preamble, sync word, header, crc checksum, et c. the configuration of the packet struct ure in tx mode is determined by the automatic packet handler (if enabled), in conjunction with a variety of packet handler registers (see table 12 on page 36). if the automatic packet handle r is disabled, the entire desired pack et structure should be loaded into fifo memory; no other fields (such as preamble or sync word are automatically added to the bytes stored in fifo memory). for further information on the configuration of t he fifos for a specific applicat ion or packet size, see "6. data handling and packet handler" on page 34. when in fifo mode, the chip will auto matically exit the tx stat e when either the ipksent or ipkvalid interrupt occurs. the chip will return to the id le mode state progr ammed in "register 07h. op erating mode and function control 1". for example, the chip may be placed into tx mode by setting the txon bit, but with the pllon bit additionally set. the chip will transmit all of the contents of the fifo and th e ipksent inte rrupt will occur. when this interrupt even t occurs, the chip will clear the txon bit and return to tune mode, as indicated by the set state of the pllon bit. if no other bits are additionally set in register 07h (besides txon initially), then the chip will return to the standby state. add r/w function/description d7 d6 d5 d4 d3 d2 d1 d0 por def. 71 r/w modulation mode control 2 trclk[1] trclk[0] dtmod[1] dtmod[0] eninv fd[8] modtyp[1] modtyp[0] 00h dtmod[1:0] data source 00 direct mode using tx data via gpio pin (gpio configuration required) 01 direct mode using tx data via sdi pin (only when nsel is high) 10 fifo mode 11 pn9 (internally generated)
si4030/31/32-b1 rev 1.1 29 4.2.2. direct mode for legacy systems that perform packet handling within an mcu or other baseband chip, it may not be desirable to use the fifo. for this scenario, a direct mode is provided which bypass es the fifos entirely. in tx direct mode, the tx modulation data is applied to an input pin of the chip and processed in "real time" (i.e., not stored in a register for transmission at a later time). a variety of pins may be configured for use as the tx data input function. furthermore, an additional pin may be required for a tx clock output function if gfsk modulation is desired (only the tx data input pin is required for fsk). two options for the source of the tx data are available in the dtmod[1:0] field, and various configurations for the source of the tx data clock may be selected through the trclk[1:0] field. the eninv bit in spi register 71h will in vert the tx data; this is most likel y useful for diagnostic and testing purposes. 4.2.2.1. direct synchronous mode in tx direct mode, the chip may be configured for synchronous or asynchronous modes of modulation. in direct synchronous mode, the rfic is configured to provide a tx clock signal as an output to the external device that is providing the tx data stream. this tx clock signal is a square wave with a frequency equal to the programmed data rate. the external modulation so urce (e.g., mcu) must a ccept this tx clock signal as an input and respond by providing one bit of tx data back to the rfic, syn chronous with one edge of the tx clock signal. in this fashion, the rate of the tx data input stream from the ex ternal source is controlled by the programmed data rate of the rfic; no tx data bits are made available at the inpu t of the rfic until requested by another cycle of the tx clock signal. the tx data bits supplied by the external source are transmitted directly in real-time (i.e., not stored internally for later transmission). all modulation types (fsk/gfsk/ ook) are valid in tx direct synchronous mode. as will be discussed in the next section, there are limits on modulation ty pes in tx direct asynchronous mode. 4.2.2.2. direct asynchronous mode in tx direct asynchronous mode, the rfic no longer cont rols the data rate of the tx data input stream. instead, the data rate is controlled only by the external tx data source; the rfic simply accepts the data applied to its tx data input pin, at whatever rate it is supplied. this means that there is no longer a need for a tx clock output signal from the rfic, as there is no synchronous "hand shaking" between the rfic a nd the external data source. the tx data bits supplied by the external source are transm itted directly in real-time (i.e., not stored internally for later transmission). it is not necessary to program the data rate parameter wh en operating in tx direct asynchronous mode. the chip still internally samples the in coming tx data stream to determine when edge transitions occu r; however, rather than sampling the data at a pre-programmed data rate, the chip now internally samples the incoming tx data stream at its maximum possible oversamp ling rate. this allows the chip to accu rately determine the timing of the bit edge transitions without prio r knowledge of the data rate. (of course, it is still necessary to program the desired peak frequency deviation.) only fsk and ook modulation types are valid in tx direct asynchronous mode; gfsk modulation is not available in asynchronous mode. this is because the rfic does not have knowledge of the supplied data rate, and thus cannot determine the appropriate gaussian lowpass filter function to apply to the incoming data. one advantage of this mode that it saves a microcontroller pin because no tx clock output function is required. the primary disadvantage of this mode is the increase in occupied spectral bandwidth with fsk (as compared to gfsk). trclk[1:0] tx data clock configuration 00 no tx clock (only for fsk) 01 tx data clock is available via gpio (g pio needs programming accordingly as well) 10 tx data clock is available via sdo pin (only when nsel is high) 11 tx data clock is available via the nirq pin
si4030/31/32-b1 30 rev 1.1 4.2.2.3. direct mode using spi or nirq pins in certain applications it may be desira ble to minimize the connections to the microcontroller or to preserve the gpios for other uses. for these cases it is possible to use the spi pins and nirq as the modulation clock and data. the sdo pin can be configured to be the data clock by programming trclk = 10. if the nsel pin is low then the function of the pin will be spi data output. if the pin is high and trclk[1:0] is 10 then during tx mode the data clock will be available on the sdo pin. if trclk[1:0] is set to 11 and no interrupts are ena bled in registers 05 or 06h, then the nirq pin can also be used as the tx data clock. the sdi pin can be configured to be the data source in tx mode if dtmod[1:0] = 01. in a similar fashion, if nsel is low the pin will function as spi data-i n. if nsel is high then in tx mode it will be the data to be modulated and transmitted. figure 9 demonstrates usin g sdi and sdo as the tx data and clock: figure 9. microcontroller connections if the sdo pin is not used for data clock then it may be programmed to be the interrupt function (nirq) by programming reg 0eh bit 3. 4.2.3. pn9 mode in this mode the tx data is generated internally using a pseudorandom (pn9 sequence) bit generator. the primary purpose of this mode is for use as a test mode to obse rve the modulated spectrum without having to provide data. nsel sdi sdo spi input don?t care spi input tx on command tx mode mod i nput tx off command spi input don?t care tx on command tx mode tx off command mod output spi input spi input spi output spi output spi output spi output spi output don?t care don?t care data clk output data clk output
si4030/31/32-b1 rev 1.1 31 5. internal functional blocks this section provides an overview some of the key blocks of the internal radio architecture. 5.1. synthesizer an integrated sigma delta ( ? ) fractional-n pll synthesizer capable of operating from 240?960 mhz is provided on-chip. the si4031/32 and si4030 co ver different frequencies. this section discusses the frequency range covered by all ezradiopro devices. using a ? synthesizer has many advantag es; it provides flexibility in choosing data rate, deviation, channel frequency, and chann el spacing. the transmit mo dulation is applied directly to the loop in the digital domain through the fractional divider which results in very precise accuracy and control over the transmit deviation. depending on the part, the pll and ? - ? modulator scheme is designed to support any desired frequency and channel spacing in the range from 240?960 mhz with a frequency resolution of 156.25 hz (low band) or 312.5 hz (high band). the transmit data rate can be programm ed between 0.123?256 kbps, an d the frequency deviation can be programmed between 1?320 khz. these parameters may be adjusted via registers as shown in "3.5. frequency control" on page 22. figure 10. pll synthesizer block diagram the reference frequency to the pll is 10 mhz. the pll utilizes a differential l- c vco, with integrated on-chip inductors. the output of the vco is fo llowed by a configurable divider whic h will divide down the signal to the desired output frequency band. the modulus of this divide r stage is controlled dynamically by the output from the ? - ? modulator. the tuning resolution is sufficient to tune to the commanded frequency with a maximum accuracy of 312.5 hz anywhere in the range between 240?960 mhz. 5.1.1. vco the output of the vco is automatically divided down to the correct output frequency depending on the hbsel and fb[4:0] fields in "register 75h. frequen cy band select." the vco integrates th e resonator inductor, tuning varactor, so no external vco components are required. the vco uses a capacitance bank to cover the wide frequency range sp ecified. the capacitance bank will automatically be calibrated every time the synthesizer is enabled. in certain fast hopping applications this might not be desirable so the vco calibration may be skipped by setting the appropriate register. 5.2. power amplifier the si4032 contains an internal integrated power amplifier (pa) capable of transmitting at output levels between ?1 and +20 dbm. the si4030/31 contains a pa which is capabl e of transmitting output levels between ?8 to +13 dbm. the pa design is single-ended and is implemented as a two stage class ce amplifier with a high efficiency when transmitting at maximum power. the pa efficiency can only be optimized at one power level. changing the output power by adjusting txpo w[2:0] will scale both th e output power and current but th e efficiency will not be constant. the pa output is ramped up and down to prevent unwanted spectral splatter. n lpf cp pfd delta- sigma fref = 10 m vco tx modulation selectable divider tx
si4030/31/32-b1 32 rev 1.1 5.2.1. output power selection with the si4032, the output power is configurable in 3 db steps with the tx pow[2:0] field in "register 6dh. tx power." extra output power can allow the use of a cheaper, smaller antenna reducing the overall bom cost. the higher power setting of the chip achiev es maximum possible range, but of cour se comes at the cost of higher tx current consumption. however, depending on the duty cycle of the system, the effect on battery life may be insignificant. contact silicon labs sup port for help in eval uating this tradeoff. the +13 dbm output power of the si4030/31 is targeted at systems that require lower output power. the pa still offers high efficiency and a range of output power from ?8 to +13 dbm. add r/w function/description d7 d6 d5 d4 d3 d2 d1 d0 por def. 6d r/w tx power txpow[2] txpow[1] txpow[0] 07h txpow[2:0] si4032 output power 000 +1 dbm 001 +2 dbm 010 +5 dbm 011 +8 dbm 100 +11 dbm 101 +14 dbm 110 +17 dbm 111 +20 dbm txpow[2:0] si4030/31 output power 000 ?8 dbm 001 ?5 dbm 010 ?2 dbm 011 +1 dbm 100 +4 dbm 101 +7 dbm 110 +10 dbm 111 +13 dbm
si4030/31/32-b1 rev 1.1 33 5.3. crystal oscillator the si4030/31/32 in cludes an integrated 30 mhz crystal oscillator with a fast start-up time of less than 600 s when a suitable parallel resonant crystal is used. th e design is differential with the required crystal load capacitance integrated on-chip to minimize the number of external components. by defau lt, all that is required off- chip is the 30 mhz crystal. the crystal load capacitance can be digitally programme d to accommodate crystals with various load capacitance requirements and to adjust the frequency of the crystal oscillator. the tuning of t he crystal load capacitance is programmed through the xlc[6: 0] field of "register 09h. 30 mhz crysta l oscillator load capacitance." the total internal capacitance is 12.5 pf and is adjustable in appr oximately 127 steps (97ff/step). the xtalshift bit is a coarse shift in frequency but is not binary with xlc[6:0]. the crystal frequency adjustment can be used to compensate for crystal production toleranc es. utilizing the on- chip temperature sensor and suitable control softwa re, the temperature depende ncy of the crystal can be canceled. the typical value of the total on-chip capa citance cint can be calculated as follows: cint = 1.8 pf + 0.085 pf x xlc[6:0] + 3.7 pf x xtalshift note that the coarse shift bit xtalshift is not binary with xlc[6:0]. the total load capacitance cload seen by the crystal can be calculated by adding the sum of all external para sitic pcb capacitances cext to cint. if the maximum value of cint (16.3 pf) is not sufficient, an external capacitor can be added for exact tuning. additional information on calculating cext and crystal selecti on guidelines is provided in ?an417: si4x3x family crystal oscillator.?. the crystal oscillator fr equency is divided down internally and may be output to the mi crocontroller through one of the gpio pins for use as the system clock. in this fashion, only one crysta l oscillator is required for the entire system and the bom cost is reduced. the available clo ck frequencies and gpio configuration are discussed further in "7.2. microcontroller clock" on page 40. the si4030/31/32 may also be driven with an external 30 mhz clock signal through the xout pin. when driving with an external reference or using a tcxo, the xtal load capacitance register should be set to 0. 5.4. regulators there are a total of four regulators integrated onto the si 4030/31/32. with the exception of the digital regulator, all regulators are designed to operate with only internal de coupling. the digital regulator requires an external 1 f decoupling capacitor. all regulators are designed to operate with an input supply voltage from +1.8 to +3.6 v. the output stage of the of pa is not connected internally to a regulator and is connected directly to the battery voltage. a supply voltage should only be connected to the vdd pins. no voltage should be forced on the digital regulator output. add r/w function/description d7 d6 d5 d4 d3 d2 d1 d0 por def. 09 r/w crystal oscillator load capacitance xtalshift xlc[6] xlc[5] xlc[4] xlc[3] xlc[2] xlc[1] xlc[0] 40h
si4030/31/32-b1 34 rev 1.1 6. data handling and packet handler the internal modem is designed to operate with a packet including a 10101... preamble structure. to configure the modem to operate with packet formats without a preamble or other legacy packet st ructures contact customer support. 6.1. tx fifo a 64 byte fifo is integrated into th e chip for tx, as shown in figure 11. "r egister 7fh. fifo access" is used to access the fifo. a burst write, as described in "3.1. serial peripheral interface (spi)" on page 15, to address 7fh will write data to the tx fifo. figure 11. fifo threshold the tx fifo has two programmable thresholds. an interrup t event occurs when the data in the tx fifo reaches these thresholds. the first threshold is the fifo almost full threshold, txaf thr[5:0]. the value in this register corresponds to the desired threshold value in number of bytes. when the data being f illed into the tx fifo crosses this threshold limit, an interrupt to the microcontroller is generated so the chip can enter tx mode to transmit the contents of the tx fifo. the second threshold for tx is the fifo almost empty thresh old, txaethr[5:0]. when the data being shifted out of the tx fifo drops below the almost empty threshol d an interrupt will be generated. the microcontroller will need to s witch out of tx mode or fill more data into the tx fifo. th e transceiver can be configured so that when the tx fifo is empty it will automatically exit th e tx state and return to one of the low power states. when tx is initiated, it will transmit the nu mber of bytes programmed into the packet length field (reg 3eh). when the packet ends, the chip will return to the state s pecified in register 07h. for example, if 08h is written to address 07h then the chip will return to the standby state. if 09h is written then t he chip will return to the ready state. tx fifo tx fifo almost empty threshold tx fifo almost full threshold
si4030/31/32-b1 rev 1.1 35 the tx fifo may be cleared or reset wit h the ffclrtx bit in ?register 08h. operating mode and function control 2.? all interrupts may be enabled by setting the interrupt enabled bits in "register 05h. interrupt enable 1" and ?register 06h. interrup t enable 2,? on page 59. if the interrupts are not e nabled the function will not generate an interrupt on the nirq pi n but the bits will still be read correctly in the interrupt status registers. 6.2. packet configuration when using the fifo, automatic packet handling may be enabled for the tx mode. "register 30h. data access control" through ?register 3eh. packet length,? on page 79 control the configuration for packet handling. the usual fields for network communication (such as preamb le, synchronization word, headers, packet length, and crc) can be configured to be automatically added to th e data payload. the fields needed for packet generation normally change infrequently and can therefore be stored in registers. automatically addi ng these fields to the data payload greatly reduces the amount of communicatio n between the microcontroller and the si4030/31/32 and reduces the required computational power of the microcontroller. the general packet structure is shown in figure 12. the leng th of each field is shown below the field. the preamble pattern is always a series of alternating ones and zero es, starting with a zero. all the fields have programmable lengths to accommodate different applications. the most common crc polynominals are available for selection. figure 12. packet structure an overview of the packet handler config uration registers is shown in table 12. 6.3. packet ha ndler tx mode if the tx packet length is set the pa cket handler will send the number of by tes in the packet le ngth field before returning to idle mode and asserting the packet sent interrupt. to resume sending data from the fifo the microcontroller needs to command the chip to re-enter tx mode. figure 14 provides an example transaction where the packet length is set to three bytes. add r/w function/d escription d7 d6 d5 d4 d3 d2 d1 d0 por def. 08 r/w operating & function control 2 reserved reserved reserved reserved autotx reserved reserved ffclrtx 00h 7c r/w tx fifo control 1 reserved reserved txafthr[5] txafthr[4] txaf thr[3] txafthr[2] txafthr[1] txafthr[0] 37h 7d r/w tx fifo control 2 reserved reserved txaethr[5] txaethr[4] txae thr[3] txaethr[2] txaethr[1] txaethr[0] 04h data preamble sync word tx header packet length crc 1-512 bytes 1-4 bytes 0-4 bytes 0 or 1 byte 0 or 2 bytes
si4030/31/32-b1 36 rev 1.1 figure 13. multiple packets in tx packet handler table 12. packet handler registers add r/w function/description d7 d6 d5 d4 d3 d2 d1 d0 por def. 30 r/w data access control reserved lsbfrst cr cdonly skip2ph enpactx encrc crc[1] crc[0] 8dh 31 r ezmac status 0 reserved reserved reserved reserved reserved pktx pksent ? 32 reserved 33 r/w header control 2 skipsyn hdlen[2] hdlen[1] hdl en[0] fixpklen synclen[1] synclen[0] prealen[8] 22h 34 r/w preamble length prealen[7] prealen[6] prealen[5] prealen[4] prealen[3] prealen[2] prealen[1] prealen[0] 08h 36 r/w sync word 3 sync[31] sync[30] sync[29] sync[28] sync[27] sync[26] sync[25] sync[24] 2dh 37 r/w sync word 2 sync[23] sync[22] sync[21] sync[20] sync[19] sync[18] sync[17] sync[16] d4h 38 r/w sync word 1 sync[15] sync[14] sync[13] sync[12] sync[11] sync[10] sync[9] sync[8] 00h 39 r/w sync word 0 sync[7] sync[6] sync[5] s ync[4] sync[3] sync[2] sync[1] sync[0] 00h 3a r/w transmit header 3 txhd[31] txhd[30] txhd[29] txhd[28] txhd[27] txhd[26] txhd[25] txhd[24] 00h 3b r/w transmit header 2 txhd[23] txhd[22] txhd[21] txhd[20] txhd[19] txhd[18] txhd[17] txhd[16] 00h 3c r/w transmit header 1 txhd[15] txhd[14] txhd[13] txhd[12] txhd[11] txhd[10] txhd[9] txhd[8] 00h 3d r/w transmit header 0 txhd[7] txhd[6] txhd[ 5] txhd[4] txhd[3] txhd[2] txhd[1] txhd[0] 00h 3e r/w transmit packet length pklen[7] pklen[6] pklen[ 5] pklen[4] pklen[3] pklen[2] pklen[1] pklen[0] 00h data 1 data 2 data 3 data 4 data 5 data 6 data 7 data 8 data 9 } } } this will be sent in the first transmission this will be sent in the second transmission this will be sent in the third transmission
si4030/31/32-b1 rev 1.1 37 6.4. data whitening, manchester encoding, and crc data whitening can be used to avoid extended sequences of 0s or 1s in the transmitted data stream to achieve a more uniform spectrum. when enabled, the payload dat a bits are xored with a pseudorandom sequence output from the built-in pn9 generator. the gene rator is initialized at th e beginning of the payload. the receiver recovers the original data by repeating this operation. manchester encoding can be used to ensure a dc-free transmission and good synchronization properties. when manchester encoding is used, the effective datarate is unchanged but the actual datarate (preamble length, etc.) is doubled du e to the nature of the encoding. the effective datarate when using manchester encoding is limited to 128 kbps. the implementati on of manchester encoding is shown in figure 15. data whitening and manchester encoding can be selected with "register 70h. modulation mode control 1". the crc is configured via "register 30h. data acce ss control". figure 14 demonstrates the portions of the packet which have manchester encoding, data whitening, and crc applied. crc can be applied to only the data portion of the packet or to the data, packet length and he ader fields. figure 15 provides an example of how the manchester encoding is done and also the use of the manchester invert (enmaniv) function. figure 14. operation of data whitening, manchester encoding, and crc figure 15. manchester coding example 6.5. synchronization word configuration the synchronization word length can be configured in reg 33h, synclen[1:0]. the expected or transmitted sync word can be configured from 1 to 4 bytes as defined below: ? synclen[1:0] = 00?transmitted synchronization word (sync word) 3. ? synclen[1:0] = 01?transmitted synchronization word 3 first, followed by sync word 2. ? synclen[1:0] = 10?transmitted synchronization word 3 fi rst, followed by sync word 2, followed by sync word 1. ? synclen[1:0] = 1?transmitted synchronization word 3 first, followed by sync word 2, followed by sync word 1, followed by sync word 0. the sync is transmitted in the following sequence: sync 3 ? sync 2 ? sync 1 ? sync 0. the sync word values can be programmed in registers 36h?39h. preamble sync header/ address pk length data crc crc (over data only) crc whitening manchester data before mancheste r data after machester ( manppol = 1, enmaninv = 0) data after machester ( manppol = 1, enmaninv = 1) data before manchester data after machester ( manppol = 0, enmaninv = 0) data after machester ( manppol = 0, enmaninv = 1) 111 11111 0 0001 000 0000 0 preamble = 0xff first 4bits of the synch. word = 0x2 preamble = 0x00 first 4bits of the synch. word = 0x2 0001 0
si4030/31/32-b1 38 rev 1.1 6.6. tx retransm ission and auto tx the si4030/31/32 is capable of automatically retransmit ting the last packet loaded in the tx fifo. automatic retransmission is set by entering the tx state with the txon bit without reloading the tx fifo. this feature is useful for beacon transmission or when retransmission is requ ired due to the absence of a valid acknowledgement. only packets that fit completely in the tx fifo can be automatically retransmitted. an automatic transmission function is available, allowing the radio to automatically start or stop a transmission depending on the amount of data in the tx fifo. when autotx is set in ?register 08. operating & function control 2," the tr ansceiver will automatically enter the tx state when the tx fifo almost full threshold is exceed ed. packets will be transmitted according to the configured packet length. to stop transmitting, clear the packet sent or tx fifo almost empty interrupts must be cleared by reading register.
si4030/31/32-b1 rev 1.1 39 7. auxiliary functions 7.1. smart reset the si4030/31/32 contains an enhanc ed integrated smart reset or por ci rcuit. the por circuit contains both a classic level threshold reset as well as a slope detect or por. this reset circuit was designed to produce a reliable reset signal under any circum stances. reset will be in itiated if any of the following conditions occur: ? initial power on, vdd starts from gnd: reset is active till v dd reaches v rr (see table); ? when v dd decreases below v ld for any reason: reset is active till v dd reaches v rr ; ? a software reset via ?register 08h. operating mode and f unction control 2,? on page 61: reset is active for time t swrst ? v dd glitch when the supply voltage exceeds the followin g time functioned limit: figure 16. por glitch parameters the reset will initialize all regist ers to their default values. the reset signal is also av ailable for output and use by the microcontroller by using the default setting for gpio_0 . the inverted reset signal is available by default on gpio_1. table 13. por parameters parameter symbol comment min typ max unit release reset voltage vrr 0.85 1.3 1.75 v power-on vdd slope svdd tested vdd slope region 0.03 ? 300 v/ms low vdd limit vld vld=0.4+t*0.2v/ms actual vdd(t) showing glitch reset limit: 0.4v+t*0.2v/ms vdd nom. 0.4v
si4030/31/32-b1 40 rev 1.1 7.2. microcontroller clock the 30 mhz crystal oscillator frequency is divided down in ternally and may be output to the microcontroller through gpio2. this feature is useful to lower bom cost by using only one crystal in the system. the system clock frequency is selectable from one of 8 options, as shown below. except for the 32.768 khz option, all other frequencies are derived by dividing th e crystal oscillator frequency. the 32.7 68 khz clock signal is derived from an internal rc oscillator or an external 32 khz crystal. the default setting for gpio2 is to output the microcontroller clock signal with a frequency of 1 mhz. if the microcontroller clock option is being used there ma y be the need of a system clock for the microcontroller while the si4030/31/32 is in sleep mode . since the crystal oscillator is disa bled in sleep mode in order to save current, the low-power 32.768 khz clock can be automatically switched to become the microcontroller clock. this feature is called enable low frequency clock and is enabled by the enlfc bit in ?regist er 0ah. microcontroller output clock." when enlfc = 1 and the chip is in sleep mode then the 32.768 k hz clock will be provided to the microcontroller as the system clock, r egardless of the setting of mclk[2:0]. fo r example, if mclk[2:0] = 000, 30 mhz will be provided through the gpio output pin to the microcontroller as the system clock in all idle or tx states. when the chip enters sleep mode, the system clock will automatically swit ch to 32.768 khz from the rc oscillator or 32.768 xtal. another available feature for the microcontroller clock is the clock tail, clkt[1:0] in ?register 0ah. microcontroller output clock." if the low frequency clock feature is not enabled (enlfc = 0), then the system clock to the microcontroller is disabled in sleep mode. however, it may be usef ul to provide a few extra cycles for the microcontroller to complete its operation prior to the shutdo wn of the system clock signal. setting the clkt[1:0] field will provide additional cycl es of the system cloc k before it shuts off. if an interrupt is triggered, the microcontroller clock will remain enabled rega rdless of the selected mode. as soon as the interrupt is read the state ma chine will then move to the selected mode. the minimum current consumption will not be achieved until the interrup t is read. for instance, if the ch ip is commanded to sleep mode but an interrupt has occurred the 30 mhz xtal will not be disabled un til the interrupt has been cleared. add r/w function/description d7 d6 d5 d4 d3 d2 d1 d0 por def. 0a r/w microcontroller output clock clkt [1] clkt[0] enlfc mclk[2] mclk[1] mclk[0] 0bh mclk[2:0] clock frequency 000 30 mhz 001 15 mhz 010 10 mhz 011 4 mhz 100 3 mhz 101 2 mhz 110 1 mhz 111 32.768 khz clkt[1:0] clock tail 00 0 cycles 01 128 cycles 10 256 cycles 11 512 cycles
si4030/31/32-b1 rev 1.1 41 7.3. general purpose adc an 8-bit sar adc is integrated for general purpose use, as well as for digitizing the on-chip temperature sensor reading. registers 0fh "adc confi guration", 10h "sensor offset" and 4fh "amplifier offset" can be used to configure the adc operation. deta ils of these registers are on pages 67 and 68, respectively. every time an adc conversion is desir ed, bit 7 "adcstart/adcbusy" in ?reg ister 1fh. clock recovery gearshift override? must be set to 1. this is a self clearing bit that will be reset to 0 at the end of the conversion cycle of the adc. the conversion time for the adc is 350 s. after this time or when the "a dcstart/adcbusy" bit is cleared, then the adc value may be read out of ?register 11h. adc value." the architecture of the adc is shown in figure 17. the signal and reference inputs of the adc are selected by adcsel[2:0] and adcref[1:0] in register 0fh ?adc configurat ion?, respectively. the default setting is to read out the temperature sensor using the bandgap voltage (vbg) as re ference. with the vbg reference the input range of the adc is from 0-1.02 v with an lsb reso lution of 4 mv (1.02/255) . changing the adc reference will change the lsb resolution accordingly. a differential multiplexer and amplifier are provided for inte rfacing external bridge sensors. the gain of the amplifier is selectable by adcgain[1:0] in regi ster 0fh. the majority of sensor bridges have supply voltage (vdd) dependent gain and offset. the reference voltage of the adc can be changed to either v dd /2 or v dd /3. a programmable v dd dependent offset voltage can be add ed using soffs[3:0] in register 10h. see ?an448: general purpose adc configuration? for mo re details on the usage of the general purpose adc. figure 17. general purpose adc architecture add r/w function/description d7 d6 d5 d4 d3 d2 d1 d0 por def. 0f r/w adc configuration adcstart/adcbusy adcsel[2] adcsel[1] adcsel[0] adcref[1] adcref[0] adcgain[1] adcgain[0] 00h 10 r/w sensor offset soffs[3] soffs[2] soffs[1] soffs[0] 00h 11 r adc value adc[7] adc[6] adc[5] adc[4] adc[3] adc[2] adc[1] adc[0] ? ? ? ? ? ? ? diff. mux diff. amp. input mux ref mux v in v ref ? ? adcsel [2:0] aoffs [4:0] adcgain [1:0] adcsel [2:0] adcref [1:0] adc [7:0] v dd / 3 v dd / 2 gpio1 gpio0 gpio2 temperature sensor v bg (1.2v) 8-bit adc 0 -1020mv / 0-255 soffs [3:0]
si4030/31/32-b1 42 rev 1.1 7.4. temperature sensor an integrated on-chip analog temperature sensor is av ailable. the temperature sensor will be automatically enabled when the temperature sensor is selected as t he input of the adc or when the analog temp voltage is selected on the analog test bus. the temperature sens or value may be digitized using the general-purpose adc and read out over the spi through "register 10h. adc s ensor amplifier offset." t he range of the temperature sensor is configurable. table 14 lists the settings for the different temperature ranges and performance. to use the temp sensor: 1. set the input for adc to the temperature sensor, "register 0fh. adc config uration"?adcsel[2:0] = 000 2. set the reference for adc, "register 0fh. adc configuration"?adcref[1:0] = 00 3. set the temperature range for adc, "register 12 h. temperature sensor calibration"?tsrange[1:0] 4. set entsoffs = 1, "register 12h. temperature sensor calibration" 5. trigger adc reading, "register 0fh. adc configuration"?adcstart = 1 6. read temperature value?read contents of "register 11h. adc value" the slope of the temperature sensor is very linear and monotonic. for absolute accuracy better than 10 c calibration is necessary. the temperature sensor may be calibrated by setting entsoffs = 1 in ?register 12h. temperature sensor control? and settin g the offset with the tvoffs[7:0] bits in ?register 13h. temperature value offset.? this method adds a positive offset digitally to th e adc value that is read in ?r egister 11h. adc value.? the other method of calibration is to us e the tstrim which compensates the anal og circuit. this is done by setting entstrim = 1 and using the tstrim[2:0] bits to offset the temperature in ?register 12h. temperature sensor control.? with this method of calibration, a negative offset may be achieved. with both methods of calibration better than 3 c absolute accuracy may be achieved. the different ranges for the temperature sensor and adc8 are demonstrated in figure 18. the value of the adc8 may be translated to a temperature reading by adc8 value x adc8 lsb + lowest temperature in temp range. for instance for a tsrange = 00, temp = adc8value x 0.5 ? 64. add r/w function/description d7 d6 d5 d4 d3 d2 d1 d0 por def. 12 r/w temperature sensor control tsrange[1] tsrange[0] entsoffs entstrim tstrim[3] tstrim[2] vbgtrim[1] vbgtrim[0] 20h 13 r/w temperature value offset tvoffs[7] tvoffs[6] tvoffs[5] tvoffs[4] tvoffs[3] tvoffs[2] tvoffs[1] tvoffs[0] 00h table 14. temperature sensor range entoff tsrange[1] tsrange[0] temp. range unit slope adc8 lsb 1 0 0 ?64 ? 64 c 8 mv/c 0.5 c 1 0 1 ?64 ? 192 c 4 mv/c 1 c 1 1 0 0 ? 128 c 8 mv/c 0.5 c 1 1 1 ?40 ? 216 f 4 mv/f 1 f 0* 1 0 0 ? 341 k 3 mv/k 1.333 k *note: absolute temperature mode, no temperature shift. this mode is only for test purposes. por value of en_toff is 1.
si4030/31/32-b1 rev 1.1 43 figure 18. temperature ranges using adc8 temperature measurement with adc8 0 50 100 150 200 250 300 - 40 - 20 0 20 40 60 80 100 temperature [celsius] sensor range 0 sensor range 1 sensor range 2 sensor range 3 adc v alue
si4030/31/32-b1 44 rev 1.1 7.5. low battery detector a low battery detector (lbd) with digital read-out is integr ated into the chip. a digital threshold may be programmed into the lbdt[4:0] field in "registe r 1ah. low battery detector threshol d." when the digitized battery voltage reaches this threshold an interrupt will be generated on the nirq pi n to the microcontroller. the microcontroller can confirm source of the interrupt by reading "register 03h. interrupt/status 1" and ?register 04h. interrupt/status 2,? on page 56. if the lbd is enabled while the chip is in sleep mode, it will automatically enable th e rc oscillator which will periodically turn on the lbd circuit to measure the battery voltage. the battery voltage may also be read out through "register 1bh. battery voltage level" at any time when the lbd is enabled. the low battery detect function is enabled by setting enlbd=1 in "register 0 7h. operating mode and function control 1". the lbd output is digitized by a 5-bit adc. when th e lbd function is enabled, enlbd = 1 in "register 07h. operating mode and function control 1", the battery volt age may be read at anytime by reading "register 1bh. battery voltage level." a battery voltage threshold may be programmed in ?register 1ah. low battery detector threshold." when the ba ttery voltage level drops below the battery vo ltage threshold an inte rrupt will be generated on the nirq pin to the microcontroller if the lbd interrupt is enabled in ?register 06h. interrupt enable 2,? on page 59. the microcontroller will then need to verify the interrupt by reading the interrupt status register, addresses 03 and 04h. the lsb step size for the lbd adc is 50 mv, with the adc range demonstrated in the table below. if the lbd is enabled the lbd and adc will automatically be enab led every 1 s for approximate ly 250 s to measure the voltage which minimizes the current consumption in sensor mode. before an interrupt is activated four consecutive readings are required. ad r/w function/description d7 d6 d5 d4 d3 d2 d1 d0 por def. 1a r/w low battery detector threshold lbdt[4] lbdt[3] lbdt[2] lbdt[1] lbdt[0] 14h 1b r battery voltage level 0 0 0 vbat[4] vbat[3] vbat[2] vbat[1] vbat[0] ? adc value vdd voltage [v] 0< 1.7 1 1.7?1.75 2 1.75?1.8 ?? 29 3.1?3.15 30 3.15?3.2 31 > 3.2 adcvalue mv tage batteryvol ? ? ? 50 7 . 1
si4030/31/32-b1 rev 1.1 45 7.6. wake-up timer the chip contains an in tegrated wake-up ti mer which can be used to periodica lly wake the chip from sleep mode. the wake-up timer runs from the internal 32.768 khz rc oscillator. the wake-up timer can be configured to run when in sleep mode. if enwt = 1 in "register 07h. operating mode and fu nction control 1" when entering sleep mode, the wake-up timer will c ount for a time specified def ined in registers 14?16h, "wake up timer period." at the expiration of this period an interr upt will be generate d on the nirq pin if this interrupt is enabled. the microcontroller will then need to verify the interrupt by reading the register s 03h?04h, "interrupt status 1 & 2". the wake-up timer value may be read at any time by the wtv[15:0] read only registers 13h?14h. the formula for calculating the wake-up period is the following: use of the d variable in the formula is only necessary if fi ner resolution is required than can be achieved by using the r value. there are two differ ent methods for utilizing the wake -up timer (wut) depending on if the wut interrupt is enabled in ?register 06h. interrupt enable 2,? on page 59. if t he wut interrupt is enabled th en nirq pin will go low when the timer expires. the chip will also change state so that the 30 mhz xtal is enabled so that the microcontroller clock output is available for the microc ontroller to use to process the interrupt. the other method of use is to not enable the wut interrupt and use the wut gpio setting. in this mode of operation the chip will not change state until commanded by the microcontroller. the different modes of operating the wut and the current consumption impacts are demonstrated in figure 19. a 32 khz xtal may also be used for better timing accuracy . by setting the x32 ksel bit in ?register 07h. operating & function control 1," gpio0 is automatically reconfigured so that an external 32 khz xtal may be connected to this pin. in this mode, the gpio0 is extremely sensitiv e to parasitic capacitance, so only the xtal should be connected to this pin with the xtal physically located as close to the pin as possible. once the x32 ksel bit is set, all internal functions such as wut, microcontroller clock, and ldc mode will use the 32 khz xtal and not the 32 khz rc oscillator. wut register description wtr[3:0] r value in formula wtd[1:0] d value in formula wtm[15:0] m value in formula add r/w function/description d7 d6 d5 d4 d3 d2 d1 d0 por def. 14 r/w wake-up timer period 1 wtr[3 ] wtr[2] wtr[1] wtr[0] wtd[1] wtd[0] 00h 15 r/w wake-up timer period 2 wtm[15] wtm[14] w tm[13] wtm[12] wtm[11] wt m[10] wtm[9] wtm[8] 00h 16 r/w wake-up timer period 3 wtm[7] wtm[6 ] wtm[5] wtm[4] wtm[3] wtm[2] wtm[1] wtm[0] 00h 17 r wake-up timer value 1 wtv[15] wtv[14] w tv[13] wtv[12] wtv[11] w tv[10] wtv[9] wtv[8] ? 18 r wake-up timer value 2 wtv[7] wtv[6] w tv[5] wtv[4] wtv[3] wtv[2] wtv[1] wtv[0] ? ms m wut r 768 . 32 2 4 ? ? ?
si4030/31/32-b1 46 rev 1.1 figure 19. wut interrupt and wut operation wut period gpiox = 00001 nirq spi interrupt read chip state current consumption sleep ready sleep ready sleep ready sleep 1 ua 1.5 ma 1.5 ma wut period gpiox = 00001 nirq spi interrupt read chip state current consumption sleep 1 ua interrupt enable enwut = 1 ( reg 06h) interrupt enable enwut = 0 ( reg 06h) 1 ua 1.5 ma 1 ua
si4030/31/32-b1 rev 1.1 47 7.7. gpio configuration three general purpose ios (gpios) are available. numerous functions such as specific interrupts, trsw control, microcontroller output, etc. can be routed to the gpio pi ns as shown in the tables below. when in shutdown mode all the gpio pads are pulled low. note: the adc should not be selected as an input to the gpio in standby or sleep modes and will cause excess current con- sumption. the gpio settings for gpio1 and gpio2 are the same as for gpio0 with the except ion of the 00000 default setting. the default settings for each gpio are listed below: for a complete list of the avai lable gpio's see ?an466: si4430 /31/32 register descriptions.? the gpio drive strength may be adjusted with the gpioxdrv[1:0 ] bits. setting a higher va lue will increase the drive strength and current capability of the gp io by changing the driver size. specia l care should be taken in setting the drive strength and loading on gpio2 wh en the microcontroller clock is used. excess loading or inadequate drive may contribute to increased spurious emissions. add r/w function/ description d7 d6 d5 d4 d3 d2 d1 d0 por def. 0b r/w gpio0 configuration gpio0drv[1] gpio0drv[0] pup0 gpio0[4] gpio0[3] gpio0[2] gpio0[1] gpio0[0] 00h 0c r/w gpio1 configuration gpio1drv[1] gpio1drv[0] pup1 gpio1[4] gpio1[3] gpio1[2] gpio1[1] gpio1[0] 00h 0d r/w gpio2 configuration gpio2drv[1] gpio2drv[0] pup2 gpio2[4] gpio2[3] gpio2[2] gpio2[1] gpio2[0] 00h 0e r/w i/o port configuration extitst[2] extitst[1] extitst[0] itsdo dio2 dio1 dio0 00h gpio 00000?default setting gpio0 por gpio1 por inverted gpio2 microcontroller clock
si4030/31/32-b1 48 rev 1.1 8. reference design reference designs are available at www.silabs.com for many common applications which include recommended schematics, bom, and layout. tx matching component va lues for the different frequency bands can be found in the application notes ?an435: si4032/4432 pa matchi ng? and ?an436: si4030/4031/4430/4431 pa matching.? %&'('
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si4030/31/32-b1 rev 1.1 49 9. application notes and reference designs a comprehensive set of application notes and reference de signs are available to assist with the development of a radio system. a partial list of applications notes is given below. for the complete list of applic ation notes, latest referenc e designs and demos visit the silicon labs website . ? an361: wireless mbus implementation using ezradiopro devices ? an379: antenna diversity with ezradiopro ? an414: ezradiopro layout design guide ? an415: ezradiopro programming guide ? an417: si4x3x family crystal oscillators ? an419: arib std-t67 narrow-band 426/429 mhz measured on the si4431-a0 ? an427: ezradiopro si433x and si443x rx lna matching ? an429: using the dc-dc converter on the f9xx seri es mcu for single battery operation with the ezradiopro rf devices ? an432: rx ber measurement on ez radiopro with a looped pn sequence ? an435: si4032/4432 pa matching ? an436: si4030/4031/ 4430/4431 pa matching ? an437: 915 mhz measurement results and fcc compliance ? an439: ezradiopro quick start guide ? an440: si4430/31/32 detailed register descriptions ? an445: si4431 rf performance and etsi compliance test results ? an448: general purpose adc configuration ? an453: using the ezradiopro calculator and advanced rx bw calculations and settings ? an459: 950 mhz measurement results and arib compliance ? an460: 470 mhz measurement results for china ? an461:+24 dbm external pa application note and reference design ? an462: extended battery life using the ezradiopro and a dc-dc buck converter ? an463: support for non-standard packet structures and raw mode ? an466: si4030/31/32 register descriptions ? an467: si4330 register descriptions 10. customer support technical support fo r the complete family of silicon labs wireless products is ava ilable by accessing the wireless section of the silicon labs' website at www.silabs.com\wireless . for answers to common q uestions please visit the wireless knowledge base at www.silabs.com/support/knowledgebase .
si4030/31/32-b1 50 rev 1.1 11. register table and descriptions note: detailed register descriptions are available in ?an466: si4030/31/32 register descriptions.? table 15. register descriptions add r/w function/desc data por default d7 d6 d5 d4 d3 d2 d1 d0 01 r device version 0 0 0 vc[4] vc[3] vc[2] vc[1] vc[0] 06h 02 r device status ffovfl ffunfl reserved reserved reserved cps[1] cps[0] ? 03 r interrupt status 1 ifferr itxffafull itxffaem reserved iext ipksent reserved reserved ? 04 r interrupt status 2 reserved reserved reserved reserved iwut ilbd ichiprdy ipor ? 05 r/w interrupt enable 1 enfferr entxffafull entxffaem reserved enext enpksent reserved reserved 00h 06 r/w interrupt enable 2 reserved reserved reserved reserved enwut enlbd enchiprdy enpor 03h 07 r/w operating & function control 1 swres enlbd enwt x32ksel txon reserved pllon xton 01h 08 r/w operating & function control 2 reserved reserve d reserved reserved autotx enldm reserved ffclrtx 00h 09 r/w crystal oscillator load capacitance xtalshft xlc[6] xlc[5] xlc[4] xlc[3] xlc[2] xlc[1] xlc[0] 7fh 0a r/w microcontroller output clock reserved reser ved clkt[1] clkt[0] enlfc mclk[2] mclk[1] mclk[0] 06h 0b r/w gpio0 configuration gpio0drv[1] gpio0drv[0] pup0 gpio0[4] gpio0[3] gpio0[2] gpio0[1] gpio0[0] 00h 0c r/w gpio1 configuration gpio1drv[1] gpio1drv[0] pup1 gpio1[4] gpio1[3] gpio1[2] gpio1[1] gpio1[0] 00h 0d r/w gpio2 configuration gpio2drv[1] gpio2drv[0] pup2 gpio2[4] gpio2[3] gpio2[2] gpio2[1] gpio2[0] 00h 0e r/w i/o port configuration reserved extitst[2] extitst[1] extitst[0] itsdo dio2 dio1 dio0 00h 0f r/w adc configuration adcstart/ adc- done adcsel[2] adcsel[1] adcsel[0] adcref[1] adcref[0] adcgain[1] adcgain[0] 00h 10 r/w adc sensor amplifier offset reserved reserved reserv ed reserved adcoffs[3] adcoffs [2] adcoffs[1] adcoffs[0] 00h 11 r adc value adc[7] adc[6] adc[5] a dc[4] adc[3] adc[2] adc[1] adc[0] ? 12 r/w temperature sensor control tsrange[1] tsrange[0] entsoffs entstrim tstrim[3] tstrim[2] tstrim[1] tstrim[0] 20h 13 r/w temperature value offset tvoffs[7] tvoffs[6] tvoffs[5] tvoffs[4] tvoffs[3] tvoffs[2] tvoffs[1] tvoffs[0] 00h 14 r/w wake-up timer period 1 reserved reserved reserved wtr[4] wtr[3] wtr[2] wtr[1] wtr[0] 03h 15 r/w wake-up timer period 2 wtm[15] wtm[14] wtm[13] wtm[12] wtm[11] wtm[10] wtm[9] wtm[8] 00h 16 r/w wake-up timer period 3 wtm[7] wtm[6] wtm[5] wtm[4] wtm[3] wtm[2] wtm[1] wtm[0] 01h 17 r wake-up timer value 1 wtv[15] wtv[14] wtv[13] wtv[12] wtv[11] wtv[10] wtv[9] wtv[8] ? 18 r wake-up timer value 2 wtv[7] wtv[6] wtv[5] wtv[4] wtv[3] wtv[2] wtv[1] wtv[0] ? 19 reserved 1a r/w low battery detector threshold reserved reserved reserved lbdt[4] lbdt[3] lbdt[2] lbdt[1] lbdt[0] 14h 1b r battery voltage level 0 0 0 vbat[4] vbat[3] vbat[2] vbat[1] vbat[0] ? 1c-2f reserved 30 r/w data access control reserved lsbfrst crcdonly reserved enpactx encrc crc[1] crc[0] 8dh 31 r ezmac status 0 reserved reserved reserved reserved reserved pktx pksent ? 32 reserved 33 r/w header control 2 reserved hdlen[2] hdlen[1] hdlen [0] fixpklen synclen[1] synclen[0] prealen[8] 22h 34 r/w preamble length prealen[7] prealen[6] prealen[5] prealen[4] prealen[3] prealen[2] prealen[1] prealen[0] 08h 36 r/w sync word 3 sync[31] sync[30] sync[29] sync[28] sync[27] sync[26] sync[25] sync[24] 2dh 37 r/w sync word 2 sync[23] sync[22] sync[21] sync[20] sync[19] sync[18] sync[17] sync[16] d4h 38 r/w sync word 1 sync[15] sync[14] sync[13] sync[12] sync[11] sync[ 10] sync[9] sync[8] 00h 39 r/w sync word 0 sync[7] sync[6] sync[5] sync[4] sync[3] sync[2] sync[1] sync[0] 00h 3a r/w transmit header 3 txhd[31] txhd[30] txhd[2 9] txhd[28] txhd[27] txhd[26] txhd[25] txhd[24] 00h 3b r/w transmit header 2 txhd[23] txhd[22] txhd[2 1] txhd[20] txhd[19] txhd[18] txhd[17] txhd[16] 00h 3c r/w transmit header 1 txhd[15] txhd[14] txhd [13] txhd[12] txhd[11] txhd[10] txhd[9] txhd[8] 00h 3d r/w transmit header 0 txhd[7] txhd[6] tx hd[5] txhd[4] txhd[3] txhd[2] txhd[1] txhd[0] 00h 3e r/w transmit packet length pklen[7] pklen[6] pklen[ 5] pklen[4] pklen[3] pklen[2] pklen[1] pklen[0] 00h 4f r/w adc8 control reserved reserved adc8[5] adc8[4] adc8[3] adc8[2] adc8[1] adc8[0] 10h 60 reserved 62 r/w crystal oscillator/control test pwst[2] pwst[1] pwst[0] clkhyst enbias2x enamp2x bufovr enbuf 24h 6d r/w tx power papeakval papeaken papeaklvl[1] pap eaklvl[0] ina_sw txpow[2] txpow[1] txpow[0] 18h 6e r/w tx data rate 1 txdr[15] txdr[14] txdr[13] txdr[12] txdr[11] txdr[10] txdr[9] txdr[8] 0ah 6f r/w tx data rate 0 txdr[7] txdr[6] txdr[5] txdr[4] txdr[3] txdr[2] txdr[1] txdr[0] 3dh 70 r/w modulation mode control 1 reserved reserved txdtrtscale enphpwdn manppol enmaninv enmanch enwhite 0ch 71 r/w modulation mode control 2 trclk[1] trclk[0] dtmod[1] dtmod[0] eninv fd[8] modtyp[1] modtyp[0] 00h 72 r/w frequency deviation fd[7] fd[6] fd[5] fd[4] fd[3] fd[2] fd[1] fd[0] 20h 73 r/w frequency offset 1 fo[7] fo[6] fo[5] fo[4] fo[3] fo[2] fo[1] fo[0] 00h 74 r/w frequency offset 2 reserved reserved res erved reserved reserved reserved fo[9] fo[8] 00h 75 r/w frequency band select reserved sbsel hbsel fb[4] fb[3] fb[2] fb[1] fb[0] 75h 76 r/w nominal carrier frequency 1 fc[15] fc[14] fc[13] fc[12] fc[11] fc[10] fc[9] fc[8] bbh 77 r/w nominal carrier frequency 0 fc[7] fc[6] fc[5] fc[4] fc[3] fc[2] fc[1] fc[0] 80h 79 r/w frequency hopping channel select fhch[7] fhch[6] fhch[5] fhch[4] fhch[3] fhch[2] fhch[1] fhch[0] 00h 7a r/w frequency hopping step size fhs[7] fhs[6] fhs[5] fhs[4] fhs[3] fhs[2] fhs[1] fhs[0] 00h 7c r/w tx fifo control 1 reserved reserved txafthr[5] txafthr[4] txafthr[3] txafthr[2] txafthr[1] txafthr[0] 37h 7d r/w tx fifo control 2 reserved reserved txaethr[5] tx aethr[4] txaethr[3] txaethr[2] txaethr[1] txaethr[0] 04h 7e reserved 7f r/w fifo access fifod[7] fifod[6] fifod[5] fifod[4] fifod[3] fifod[2] fifod[1] fifod[0] ?
si4030/31/32-b1 rev 1.1 51 12. pin descripti ons: si4030/31/32 pin pin name i/o description 1 vdd_rf vdd +1.8 to +3.6 v supply voltage input to all analog +1.7 v regulators. the recommended v dd supply voltage is +3.3 v. 2 tx o transmit output pin. the pa output is an open-dr ain connection so the l-c match must supply vdd (+3.3 vdc nominal) to this pin. 3?6 nc ? no connect. 7 gpio_0 i/o general purpose digital i/o that may be confi gured through the registers to perform various functions including: microcontroller clock ou tput, fifo status, por, wake-up timer, low battery detect, trsw, antdiversity control, etc. see the spi gpio conf iguration registers, address 0bh, 0ch, and 0dh for more information. 8 gpio_1 i/o 9 gpio_2 i/o 10 vr_dig o regulated output voltage of the digital 1.7 v regulator. a 1 f decoupling capacitor is required. 11 nc ? internally this pin is tied to the paddle of the package. this pin should be left unconnected or connected to gnd only. 12 vdd_dig vdd +1.8 to +3.6 v supply voltage input to the digital +1.7 v regulator. the recommended v dd supply voltage is +3.3 v. 13 sdo o 0?v dd v digital output that provides a serial readba ck function of the internal control registers. 14 sdi i serial data input. 0?v dd v digital input. this pin provides the seri al data stream for the 4-line serial data bus. 15 sclk i serial clock input. 0?v dd v digital input. this pin pr ovides the serial data cl ock function for the 4-line serial data bus. data is clocked into the si4030/31/32 on positive edge transitions. 16 nsel i serial interface select input. 0? v dd v digital input. this pin provides the select/enable function for the 4- line serial data bus. the signal is al so used to signify burst read/write mode. 17 nirq o general microcontroller interrupt status output. when the si4030/31/32 exhibits anyone of the interrupt events the nirq pin will be set low=0. please see t he control logic registers section for more information on the interrupt events. the microcontroller can then determine the state of the interrupt by reading a cor- responding spi interrupt status registers, address 03h and 04h. no external resistor pull-up is required, but it may be desirable if multiple interrupt lines are connected. 18 xout o crystal oscillator output. connect to an external 30 mhz crystal or to an external source. if using an external source with no crystal then dc coupling wi th a nominal 0.8 vdc level is recommended with a min- imum amplitude of 700 mvpp. 19 xin i crystal oscillator input. connect to an external 30 mhz crystal or leave fl oating when driving with an external source on xout. 20 sdn i shutdown input pin. 0?v dd v digital input. sdn should be = 0 in all modes except shutdown mode. when sdn =1 the chip will be completely shutdown and the contents of the registers will be lost. pkg paddle_gnd gnd the exposed metal paddle on the bottom of the si4030/31/32 supplies the rf and circuit ground(s) for the entire chip. it is very important that a good solder connection is made between this exposed metal paddle and the ground plane of the pcb underlying the si4030/31/32. gnd pad 1 2 3 17 18 19 20 11 12 13 14 6 7 8 9 4 5 16 10 15 xout vr_dig sclk sdi sdo vdd_dig nc vdd_rf nc gpio_2 gpio_1 nc tx nc nirq sdn xin nsel gpio_0 nc
si4030/31/32-b1 52 rev 1.1 13. ordering information part number* description package type operating temperature si4030-b1-fm ism ezradiopro transmitter qfn-20 pb-free ?40 to 85 c si4031-b1-fm ism ezradiopro transmitter qfn-20 pb-free ?40 to 85 c SI4032-B1-fm ism ezradiopro transmitter qfn-20 pb-free ?40 to 85 c *note: add an ?(r)? at the end of the device part number to denote tape and reel option; 2500 quantity per reel.
si4030/31/32-b1 rev 1.1 53 14. package markings (top marks) 14.1. si4030/31/32 top mark 14.2. top mark explanation mark method: yag laser line 1 marking: x = part number 0 = si4030 1 = si4031 2 = si4032 line 2 marking: r = die revision b = revision b1 ttttt = internal code internal tracking code. line 3 marking: yy= year ww = workweek assigned by the assembly hous e. corresponds to the last significant digit of the year and workweek of the mold date.
si4030/31/32-b1 54 rev 1.1 15. package outline: si4030/31/32 figure 21 illustrates the package details for the si4030/31/32. table 16 lists th e values for the dimensions shown in the illustration. figure 21. 20-pin quad flat no-lead (qfn) table 16. package dimensions symbol millimeters min nom max a 0.800.850.90 a1 0.00 0.02 0.05 b 0.180.250.30 d 4.00 bsc d2 2.55 2.60 2.65 e 0.50 bsc e 4.00 bsc e2 2.50 2.60 2.70 l 0.300.400.50 aaa ? ? 0.10 bbb ? ? 0.10 ccc ? ? 0.08 ddd ? ? 0.10 eee ? ? 0.10 notes: 1. all dimensions are shown in millimeters (mm) unless otherwise noted. 2. dimensioning and tolerancing per ansi y14.5m-1994. 3. this drawing conforms to the jedec solid state outline mo-220, variation vggd-8. 4. recommended card reflow profile is per the jedec/ipc j-std-020 specification for small body components.
si4030/31/32-b1 rev 1.1 55 16. pcb land pattern: si4030/31/32 figure 22 illustrates the pcb land patter n details for the si4030/31 /32. table 17 lists the values for the dimensions shown in the illustration. figure 22. pcb land pattern
si4030/31/32-b1 56 rev 1.1 table 17. pcb land pattern dimensions symbol millimeters min max c1 3.90 4.00 c2 3.90 4.00 e 0.50 ref x1 0.20 0.30 x2 2.65 2.75 y1 0.65 0.75 y2 2.65 2.75 notes: general 1. all dimensions shown are in mil limeters (mm) unless otherwise noted. 2. this land pattern design is based on ipc-7351 guidelines. note: solder mask design 1. all metal pads are to be non-solder mask defined (nsmd). clearance between the solder mask and the metal pad is to be 60 m minimum, all the way around the pad. notes: stencil design 1. a stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be used to assure good solder paste release. 2. the stencil thickness shou ld be 0.125 mm (5 mils). 3. the ratio of stencil aperture to land pad size should be 1:1 for the perimeter pads. 4. a 2x2 array of 1.10 x 1.10 mm openings on 1.30 mm pitch should be used for the center ground pad. notes: card assembly 1. a no-clean, type-3 solder paste is recommended. 2. the recommended card reflow profile is per the jedec/ipc j-std-020 specification for small body components.
si4030/31/32-b1 rev 1.1 57 d ocument c hange l ist revision 1.0 to revision 1.1 ? corrected typo under features/low power consumption on page 1.
si4030/31/32-b1 58 rev 1.1 c ontact i nformation silicon laboratories inc. 400 west cesar chavez austin, tx 78701 tel: 1+(512) 416-8500 fax: 1+(512) 416-9669 toll free: 1+(877) 444-3032 please visit the silicon labs technical support web page: https://www.silabs.com/support/pages/contacttechnicalsupport.aspx and register to submit a technical support request. silicon laboratories and silicon labs are trademarks of silicon laboratories inc. other products or brandnames mentioned herein are trademarks or registered trademarks of their respective holders. the information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice. silicon laboratories assumes no responsibility for errors and omissions, and disclaims responsib ility for any consequences resu lting from the use of information included herein. a dditionally, silicon laboratorie s assumes no responsibility for the functioning of und escribed features or parameters. silicon laboratories reserves the right to make changes without further notice . silicon laboratories makes no wa rranty, rep- resentation or guarantee regarding the suitability of its products for any particular purpose, nor does silicon laboratories as sume any liability arising out of the application or use of any product or circuit, and s pecifically disclaims any an d all liability, including wi thout limitation conse- quential or incidental damages. silicon laborat ories products are not designed, intended, or authorized for use in applications intended to support or sustain life, or for any other application in which the failure of the silicon laboratories product could create a s ituation where per- sonal injury or death may occur. should buyer purchase or us e silicon laboratories products for any such unintended or unauthor ized ap- plication, buyer shall indemnify and hold silicon laboratories harmless against all claims and damages.

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